Integrated circuits are typically packaged before they are used with other components as part of a larger electronic system. Ball grid array (BGA) packages, for example, are constructed with die mounted on a substrate, and an array of solder balls mounted on the bottom of the substrate are used to attach the package to a PC board or motherboard. In contrast, molded plastic packages use lead frames on the outer edges of the package substrate to attach the package to the PC board.
In order to test the reliability of the integrated circuit packages, the packages are subjected to multiple electrical stress tests. To perform some types of tests, metallization routing is used to bridge package substrate traces, creating simple electrical “loops” between pairs of BGA balls or lead frames. These electrical loops are commonly referred to as daisy chain loops.
One procedure performed on the IC package during reliability stress testing is to oppositely bias parallel connected daisy chain loops and measure cumulative leakage between the parallel loops. Although the leakage test is a simple one, almost all stress testing performed today is done with the use of an expensive Automatic Electrical Tester (ATE) and an expensive Device Under Test (DUT) circuit board. The purpose of an ATE is to functionally test the die in the IC package and is programmable. Therefore, an ATE is both complicated and expensive.
Using such a complicated and expensive tester to perform simple leakage testing and other such test is an inefficient use of resources that cost semiconductor manufacturers time and money. For example, a typical ATE may cost between $1 million to $5 million dollars. In addition, a DUT board may cost between $8,000 and $12,000 for each IC package design. Thus, it is not uncommon for a semiconductor manufacture to spend $350,000 a year for DUT boards. In addition, there is a current time factor of 4 days between the time the sample is submitted for the ATE test and the results are obtained.
Accordingly, what is needed is an improved method and system for performing leakage testing on IC packages that eliminates the need to use an expensive and time-consuming ATE tester. The present invention addresses such a need.